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MT1020A
BluetoothTM Baseband Controller Product Brief
Features
* * * * * * * * * * * Bluetooth v1.1 compliant Link Controller Programmable Radio Interface including BlueRF Full Bluetooth Protocol Stack up to HCI Full Duplex Audio CODEC including filtering Linear PCM to log PCM and CVSD conversion Advanced Block Power Management Embedded ARM7TDMITM Microcontroller Core Configurable l/O supply 1.8 to 3.6V 1.8V internal supply option for Low Power IP Hardware and Software available for embedded applications Single CPU Bluetooth system capability
PB5630 ISSUE 2.0 September 2001
Ordering Information MT1020A/IG/BP1N 121-pin SSBGA based microcontroller with on-chip memory, a full duplex voice CODEC and a dedicated Bluetooth Baseband Peripheral (BBP) block. The BBP implements all the time-critical elements of Bluetooth communication in hardware, with minimal involvement by the microcontroller. Relieving the on-chip processor of these repetitive tasks makes it possible for the MT1020A to run entire applications without an external host processor. A UART Interface is provided for use when operation with an an external host processor is required. Comprehensive power management maximises battery life for portable applications making the MT1020A particularly suitable for low power applications, especially those involving voice traffic.
Applications
* * * * * *
Wireless Headsets Wireless Accessories Cellular Phones Automotive PDA, Laptop Computers Digital Cameras
Description
The MT1020A is a complete Bluetooth baseband processor It combines an advanced ARM7TDMI
Mic
Earphone
Linear PCM
Host UART
m o .c U t4 e e h S ta a .D w w w
Absolute Maximum Ratings
Supply voltage (VDD ) Input voltage Output voltage Static discharge (HBM)* Storage temperature, TSTG
AUDIO CODEC QUEUE MANAGEMENT BLOCK BUFFER RAM BLUETOOTH LINK CONTROLLER VOICE ENCODING TRANSLATOR HOST UART HOST INTERFACE SYSTEM BUS INTERFACE
-0.5V to +5V -0.5V to OpV DD +0.5V -0.5V to OpV DD +0.5V 2kV -55C to +150C * Human Body Model
Radio Interface
Bluetooth Baseband Peripheral (BBP) Block
System RAM
External Memory Bus
Embedded Microcontroller
GPIO
GPIO
Ext'l Ints
Interrupt Controller
Watchdog
Memory/Peripheral Controller
UART1
UART1
BSIO
BSIO
DMA
Timer/ counter
ARM7TDMI
SSM
Test & Debug
Figure 1 - MT1020A Block Diagram
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MT1020A
Preliminary Information
Figure 2 - Pin Connections
Signal Name
Pin (see notes)
I/O Type
Qty
Description
Memory/Peripheral Interface SADD[18:0] A8: A9: C8: D3: E4: G10: G8: G9: H10: H4: H9: J1: J2: J4: K1: K2: K4: L3: L4 C9: F7: B9: C6: B1: C7: D4: D7: F9: D8: B8: E7: D6: C3: C2: B7 B6: E6 A1 K3: L2 B5 D2 O(hd) 19 System Address
SDATA[15:0]
I/O(hd)
16
System Data Bus
NSCS[1:0] NSCS[3] NSWE[1:0] NSOE NSUB
O(hd) O(hd) O(hd) O(hd) O
2 1 2 1 1
Active low System Chip Select 1 and 0 Active low System Chip Select 3 Active low System Write Enable 1 and 0 Active low System output enable Active low System Upper Byte (for 16-bit RAM)(SADD[0] = lower byte) System Wait. Extended MPC access
SWAIT UART1 U1RXD U1TXD U1RTS U1CTS Host Interfaces HST_UART_RXD
F10
I(pd)
1
F3 E3 F4 E2
I(hd) O O I(hd)
1 1 1 1
UART1 Receive Data UART1 Transmit Data UART1 Ready to Send (active low1) UART1 Clear to Send (active low1)
C5
I(hd)
1
Serial Host Interface Receive Data
Table 1 - Pin Descriptions
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Preliminary Information
Signal Name HST_UART_TXD HST_UART_RTS HST_UART_CTS Reserved Reserved Serial I/O BSIO_SS BSIO_DATA_O BSIO_DATA_I BSIO_CLK General Purpose IO GPIO[7] EXTINT[2] GPIO[6] EXTINT[1] GPIO[5] GPIO[4] GPIO[3] GPIO[2] INTNSCS0 GPIO[1] BBPWAKE GPIO[0] Mode Control NICE NTRST TEST NSRESET Diagnostics TCK BDIAG[0] TDI BDIAG[1] TDO BDIAG[2] TMS BDIAG[3] H3 I/O 1 G4 O 1 H2 I/O 1 G5 I/O 1 ICE Test clock input or Xdiag[0] output ICE Test data input or Xdiag[1] output ICE Test data output or Xdiag[2] output ICE Scan test mode input or Xdiag[3] output J9 J3 H8 H11 I(pu) I(pu) I(pd) I 1 1 1 1 C11 I/O(hd) 1 D9 I/O(hd) 1 E10 E9 E8 D10 I/O(hd) I/O(hd) I/O(hd) I/O(hd) 1 1 1 1 F6 I/O(hd) 1 F8 I/O(hd) 1 General purpose I/O plus External interrupt 2 input General purpose I/O plus External interrupt 1 input General purpose I/O plus General purpose I/O plus General purpose I/O plus General purpose I/O C10 B11 B10 A11 O O I(hd) O 1 1 1 1 Serial I/O Block Slave Select Serial I/O Block Data Output Serial I/O Block Data Input Serial I/O Block Clock Output Pin (see notes) D5 C4 A3 A2 B3 I/O Type O O I/O(hd) I/O I/O Qty 1 1 1 1 1 Description
MT1020A
Serial Host Interface Transmit Data Serial Host Interface Ready to Send Serial Host Interface Clear to Send Tie to OPVDD Tie to GND
During reset input selects int/ext NSCS0 General purpose I/O plus Optional external BBP wake up input General purpose I/O
Diagnostic or ICE mode ('0' = ICE mode) Xpins/diag. Mode or ICE reset Test enable DO NOT CONNECT System reset
Table 1 - Pin Descriptions (continued)
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MT1020A
Signal Name Radio Interface RI_SYS_CLK RI_CTR3 RI_TXDRXD
Preliminary Information
Pin (see notes) I/O Type Qty Description
L7 J7 G6
I I/O I/O(hd)
1 1 1
System Clock Input Bi-directional Radio Interface Control Signal 3 Radio Transmit Data Output. (Receive Data input in Bi-Di pin mode)
RI_RXD
L5
I
1
Radio Receive Data Input (Uni-directional pin mode)
RI_NRESET RI_CTR2 RI_NSEN RI_SBBO RI_SBBI RI_SCLK RI_CTR1 RI_CTR0 Linear PCM Interface LIN_PCM_IN LIN_PCM_OUT LIN_PCM_FRM LIN_PCM_CLK CODEC Interface EAR_PLUS EAR_MINUS MIC_MINUS MIC_PLUS VREF
K8 G7 H7 L6 J6 H6 H5 J5
I/O(pu) I/O O I/O I O I/O(pd) O
1 1 1 1 1 1 1 1
Radio Reset Bi-directional radio interface control signal 2 Active low radio serial interface enable Radio Serial Transfer Data Output Radio Serial Transfer Data Input Radio Serial Transfer Clock Bi-directional Radio Interface Control Signal 1 Bi-directional Radio Interface Control Signal 0
F2 F5 G3 G2
I(hd) O I/O(hd) I/O(hd)
1 1 1 1
16bit Linear PCM Input stream 16bit Linear PCM Output stream 16bit Linear PCM Frame Sync Master / Slave 16bit Linear PCM Clock Master / Slave
J11 J10 L9 K9 K10
AO AO AI AI AO
1 1 1 1 1
Earpiece audio positive differential output Earpiece audio negative differential output Microphone audio negative differential input Microphone audio positive differential input Audio CODEC Vref decoupling capacitor pin; 100nF to AGND
PLL Analogue Test PLL_AT1 E5 1 Phase Lock Loop 1 Analogue Test Pin DO NOT CONNECT Power Supplies GNDP VDDP GND L11 K11 A6: B2: D1: D11: F1: G11: K6 L8 1 1 7 CODEC Output amplifier ground CODEC Output amplifier VDD Common Ground
VDDA
1
CODEC Analog VDD
Table 1 - Pin Descriptions (continued)
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Preliminary Information
Signal Name SUBGND Pin (see notes) A4: A10: J8: L1: L10 A7: C1: F11: H1 K5 A5: E1: E11: G1: K7 B4 I/O Type Qty 5 Analog Ground Description
MT1020A
OPVDD
4
System I/O VDD
RIVDD LAVDD
1 5
Radio Interface VDD Core VDD
PLL_VDD
1
Phase Lock Loop VDD
Note: The UART CTS and RTS signals(U1RTS, U1CTS, HST_UART_RTS & HST_UART_CTS) are all active low at the chip, but become active high after passing through a RS232 line driver IC. Key I O I/O pu pd hd to Signal Types: input Output Bidirectional Internal Pull-up Internal Pull-down Internal Peripheral HOLD cell: holds the previous voltage level of an input, until the weak drive of the hold cell is overdriven by normal drive output. This can be either as part of a MT1020A bi-directional peripheral cell or an external device.
Table 1 - Pin Descriptions (continued)
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MT1020A
Preliminary Information
Electrical Characteristics
These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges, unless otherwise stated.
Value Characteristic Min. DC Characteristics Logic supply voltage CODEC supply voltage Supply current Dynamic Power Consumption SCO connection HV3 packets utilising 1s interval sniff. Internal CODEC. SCO connection HV1 packets utilising 1s interval sniff. Internal CODEC. ACL connection utilising 1s interval sniff, no data transfer. 18 mW VDDA, VDDP, RIVDD & OPVDD =3.0V LAVDD =2.0V Temperature 25C System clock and BBP clock frequency = 5 MHz. 12 mW 1.8 2.7 40 3.6 3.6 V V A TAMB= -40C to +85C Typ. Max. Units Conditions
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mW
Normal Operating Conditions
Value Characteristic Min. Core supply voltage, LAVDD I/O supply voltage, OPVDD Radio Interface supply voltage, RIVDD CODEC supply voltages, VDDP & VDDA Input voltage Output voltage DC current per bond pad Ambient temperature 1.8 1.8 1.8 2.7 0.0 0.0 -40 Max. 3.6 3.6 3.6 3.6 OpVDD OpVDD 30 +85 V V V V V V mA C Units
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Preliminary Information
Circuit Description
General The MT1020A is a complete Bluetooth Baseband processor. When used with the Zarlink-supplied firmware and an appropriate radio transceiver it forms a complete low power Bluetooth solution. The MT1020A features : * * * * ARM7TDMI Embedded Microcontroller Dedicated Bluetooth Baseband Peripheral block Full Duplex Audio CODEC 20KB System RAM
MT1020A
data. Packets are assembled/decoded with preamble, sync words, headers and CRCs. Data whitening is performed; encryption is optional. Queue Manager Block This block performs intelligent DMA transfers between a dedicated Bluetooth data buffer RAM and the Bluetooth link controller, the host interface and the voice interface. It understands and translates between different Bluetooth packet formats, and performs payload data queue management. The MT1020A has 12KB of Data Buffer RAM. Host Interface The host interface manages the communication between the MT1020A and an external host processor. It handles the assembly and decoding of Host Controller Interface (HCI) packets. The MT1020A supports communication with the external host using a high speed host UART. Audio CODEC The full duplex CODEC includes a microphone amplifier and earpiece driver, together with filtering to ITU-T G712.
Low Power Architecture The architecture is designed for ultra low power applications. This is achieved by: * Minimising the processor overhead, allowing internal system clock speeds to be reduced to as low as 5MHz Having a dedicated Bluetooth bus for data packet DMA transfers A system partition that decodes Bluetooth packets in hardware Operating internal core with a 2V supply Low-power CODEC for voice applications
* * * *
Embedded Microcontroller Core
The Embedded Microcontroller, in addition to configuring and controlling the Bluetooth Baseband Peripheral block, has the capability to run complete applications, including the Bluetooth Protocol Stacks. This capability eliminates the need for an external host processor, making the MT1020A particularly suitable for stand-alone applications, where an external processor is not available. The Microcontroller consists of an ARM7TDMI CPU and the following general purpose peripheral blocks : * * * * * * Peripheral Controller Serial I/O Interrupt Controller 2 Counter/Timers DMA Controller UART
Bluetooth Baseband Peripheral
The Bluetooth Baseband Peripheral (BBP) sub system performs all time critical Bluetooth operations, with minimal processor overhead. It works as a slave peripheral device connected to the on-board Microprocessor. The block includes the Link Controller hardware required to communicate with other Bluetooth devices via a radio IC, a queue manager system with RAM to store packets of data, a host interface and a CODEC. Once configured, the Bluetooth Baseband Peripheral block can automatically transport packets between a host interface and the Bluetooth radio, without interaction with the processor Bluetooth Link Controller The Bluetooth Link Controller controls the Bluetooth radio. The Link controller has a programmable Radio interface enabling it to work with a number of different Bluetooth Radio Transceivers. Within the Link Controller payload data is assembled into data packets for transmission and extracted from received
ARM7TDMI Processor The ARM7TDMI RISC processor contains the ARM7 32-bit core and with the Thumb(R) instruction decompressor supporting 16-bit instructions, debug extensions, fast multiplier and the ICEBreakerTM extension.
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MT1020A
Preliminary Information
Universal Asynchronous Receiver Transmitter (UART1) The full duplex asynchronous channel provides an RS232 type interface, which supports both hardware handshaking and XON/XOFF software protocols. The Receive and Transmit channels are double buffered. UART1 may be polled, or may use an interrupt scheme for module bus transfers. An internal baud rate generator can provide selectable data rates, derived from on-chip sources for an Rx/ Tx pair. Directly triggered DMA transfers with the UART are also possible without the need for CPU intervention.
Memory/Peripheral Controller The Memory/Peripheral Controller (MPC) is the main gateway between the internal and external bus systems. It allows dynamic bus sizing and generates all control signals to access peripheral components. The MPC also supports fly-by DMA between all combinations of internal and external modes. Serial I/0 The Serial (BSIO) I/0 block supports the serial interface to a variety of external devices, such as serial EEPROM, NVRAM and Flash. It is compatible with two common interfaces: * MICROWIRETM for use with memory and peripheral devices supporting the MICROWIRE standard * SPI microcontroller serial interface The block operates in either Interrupt or Polled modes also supports Fly-by DMA transfers. Interrupt Controller (INTC) The ARM7TDMI core accepts two types of interrupt: Normal (IRQ) and Fast (FIQ). All Interrupts can be switched between types, depending upon the relative priorities required. The INTC is the central control logic that decodes the priority level and handles interrupt request signals from a total of 8 fixed predefined sources within the microcontroller core and two external sources, Gpio<7:6>. External interrupts can be set for edge or level sensitivity with a polarity option. To minimize interrupt latency, there is a hard-wired priority scheme for each channel for both FIQ and IRQ; alternatively this can be ignored and the priority assessment handled in software. Timers Two dual independent 32-bit timer/counters, with an 8-bit prescaler capability for each counter, are provided (Timers 1A, 1B, 2A and 2B). These are synchronous to the system clock and may be polled, or set up to generate interrupts on over-run, with auto-reload. DMA Controller Two DMA engines are available in the controller. These may be configured as a pair to provide a memory-to-memory DMA capability between any two locations in the ARM7TDMI memory space. Alternatively, they may be used independently for fly by transfers between off-core requesters and either on-core or off-core locations. Single or multiple byte transfers (Demand or Burst Mode) are supported and may be word, half-word or byte wide.
System Debug Options
The microcontroller core allows for two sophisticated methods of hardware and software debug. The designer should choose which methods are required. The options are: * * ARM7TDMITM Debug Interface, via the ARM MultiICETM module, or equivalent Logic Analyser coupled with an Inverse Assembler and Zarlink's Diagnostic Broadcast feature
Baseband Protocol Stack
The MT1020A is supplied with the Zarlink baseband protocol stack software. This stack, when used in conjunction with the Bluetooth Baseband Peripheral block, implements the Bluetooth Specification v1*1 up to the HCI layer. Features of the Stack include : Link Controller The Link Controller includes multi-point capability, support for multi-slot packets, and Authentication and Encryption. Link Manager Supports Park, Hold and Sniff modes for reduced power consumption. Host Controller Interface Operates a UART interface, supporting ACL (asynchronous) and SCO (synchronous) data types.
"BLUETOOTH" is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed to Zarlink Semiconductor. Thumb is a registered trademark of ARM Limited. ARM7TDMI and EmbeddedlCE are trademarks of ARM Limited. MICROWIRE is a registered trademark of National Semiconductor Corp.
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